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K4C89363AF
Network-DRAM-II Specification Version 0.0
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REV. 0.0 Nov. 2002
K4C89363AF
Revision History
Version 0.0 (Nov. 2002) - First Release
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REV. 0.0 Nov. 2002
K4C89363AF
2,097,152-WORDS x 4 BANKS x 36-BITS DOUBLE DATA RATE Network-DRAM
DESCRIPTION
K4C89363AF is a CMOS Double Data Rate Network-DRAM containing 301,989,888 memory cells. K4C89363AF is organized as 2,097,152-words x 4 banks x36 bits. K4C89363AF feature a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. K4C89363AD can operate fast core cycle compared with regular DDR SDRAM. K4C89363AF is suitable for Server, Network and other applications where large memory density and low power consumption are required. The Output Driver for Network-DRAM is capable of high quality fast data transfer under light loading condition.
FEATURES
K4C89363AF Parameter F6 CL = 4 tC K C l o c k C y c l e T i m e ( m i n ) CL = 5 CL = 6 tRC R a n d o m R e a d / W r i t e C y c l e T i m e ( m i n ) tR A C R a n d o m A c c e s s T i m e ( m i n ) ID D 1 S O p e r a t i n g C u r r e n t ( s i n g l e b a n k ) ( m a x ) ID D 2 S P o w e r D o w n C u r r e n t ( m a x ) ID D 3 S S e l f - R e f r e s h C u r r e n t ( m a x ) * Fully Synchronous Operation - Double Data Rate (DDR) - Data input/output are synchronized with both edges of DS / QS. - Differential Clock (CLK and C L K ) inputs - C S, FN and all address input signals are sampled on the positive edge of CLK. - Output data (DQs and QS) is aligned to the crossings of CLK and CLK. * Fast clock cycle time of 3.0 ns minimum - Clock : 333 MHz maximum - Data : 666 Mbps/pin maximum * * * * * * * * * Quad Independent Banks operation Fast cycle and Short Latency Selectable Data Strobe(Uni/Bi-directional data strobe) Distributed Auto-Refresh cycle in 3.9us Self-Refresh Power Down Mode Variable Write Length Control Write Latency = C A S Latency-1 Programable C A S Latency and Burst Length - C A S Laatency = 4, 5, 6 - Burst Length = 2,4 * * * * * * * Organization : 2,097,152 words x 4 banks x 36 bits P o w e r S u p p l y V o l t a g e V DD : 2 . 5 V 0 . 1 2 5 V V DDQ : 1 . 8 V 0 . 1 V 1.8V CMOS I/O comply with SSTL - 1.8 (half strength driver) Package : 144Ball BGA, 1mm x 0.8mm Ball pitch JTAG(for x36) Notice : Network-DRAM is trademark of Samsung Electronics., Co LTD 4.0 ns 3.33 ns 3.0ns 20.0 ns 20.0 ns TBD TBD TBD FB 4.5 ns 3.75 ns 3.33 ns 22.5 ns 22.5 ns TBD TBD TBD F5 5.0 ns 4.5 ns 4.0 ns 25 ns 25 ns TBD TBD TBD
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1
2
3
4
5
6
7
8
9
10
11
12
I nd ex
Pin
PD
FN
CS
Pin Names
DQ0 ~ DQ35
CLK, CLK
A0 ~ A14
BA0, BA1
A
VDD V SS V SS VDD V D DQ DQ 17 D Q1 6 V DD Q
VDD
VS S
V SS
VDD
K4C89363AF
ball pitch=1.0 x 0.8mm
B
Clock Input Chip Select
VS S Q DQ 15 D Q1 4 V SS Q
V DD Q
D Q1
D Q0
VD D Q
C
V SS Q
D Q3
D Q2
V SS Q
Address Input
Bank Address
Function Control
Data Input/Output
D
V D DQ DQ 13 D Q1 2 V DD Q VS S Q DQ 11 D Q1 0 V SS Q
V DD Q
D Q5
D Q4
VD D Q
Name
Power Down Control
E
V D DQ D Q9 LD S V DD Q
V SS Q
D Q7
D Q6
V SS Q
PIN ASSIGNMENT (TOP VIEW)
F
VS S Q /C L K V R EF V SS Q
V DD Q
LQ S
D Q8
VD D Q
G
V SS Q
FN
/CS
VS S Q
VDD
V REF
V SSQ
-4VS S CLK /P D VS S VDD A 11 A 12 VDD VS S A8 A9 VS S VDD A6 A7 VDD V D DQ A4 A5 V DD Q VS S Q DQ 26 UDS V SS Q V D DQ DQ 24 D Q2 5 V DD Q VS S Q DQ 22 D Q2 3 V SS Q V D DQ DQ 20 D Q2 1 V DD Q VS S Q DQ 18 D Q1 9 V SS Q VDD V SS TC K TM S
V DDQ
H
VSS
VS S
A1 4
A 13
VSS
Pin
NC
J
VDD
B A0
BA 1
VDD
Ground
K
VS S
A1 0
A0
VSS
Power (+2.5V)
No Connection
L
VDD
A1
A2
VDD
Reference Voltage
Name
Ground(for I/O buffer)
M
V DD Q
A3
NC
VD D Q
Power (+1.8V)(for I/O buffer)
N
V SS Q
UQ S
D Q2 7
V SS Q
P
V DD Q
D Q 28
D Q2 9
VD D Q
R
V SS Q
D Q 30
D Q3 1
V SS Q
T
V DD Q
D Q 32
D Q3 3
VD D Q
U
V SS Q
D Q 34
D Q3 5
V SS Q
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V
TD 1
TD 0
V SS
VDD
K4C89363AF
Block Diagram
CLK CLK PD
DLL CLOCK BUFFER To Each Block
BANK #3 CS FN COMMAND DECODER CONTROL SIGNAL GENERATOR BANK #2
BANK #0
ROW DECODER
MODE REGISTER A0 ~ A14 BA0, BA1 ADDRESS BUFFER UPPER ADDRESS LATCH
MEMORY CELL ARRAY
COLUMN DECODER
REFRESH COUNTER
LOWER ADDRESS LATCH
BURST COUNTER
WRITE ADDRESS LATCH ADDRESS COMPARATOR
READ DATA BUFFER
WRITE DATA BUFFER
DS QS
DQ BUFFER
DQ0 ~ DQ35
Note : The K4C89363AD configuration is 4 Bank of 16384 x 128 x 36 of cell array with the DQ pins numbered DQ0~DQ35.
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D AT A C O NT R O L A N D L A T C H C IR CU IT
BANK #1
K4C89363AF
Absolute Maximum Ratings
Symbol V DD V DDQ V IN VOUT VREF TOPR T STG T SOLDER PD IO U T Parameter Power Supply Voltage Power Supply Voltage (for I/O buffer) Input Voltage DQ pin Voltage Input Reference Voltage Operating Temperature Storage Temperature Soldering Temperature(10s) Power Dissipation Short Circuit Output Current Rating -0.3 ~ 3.3 -0.3 ~ V DD + 0.3 -0.3 ~ V DD + 0.3 -0.3 ~ V DDQ + 0.3 -0.3 ~ V DDQ + 0.3 0 ~ 70 -55 ~ 150 260 2 50 Units V V V V V
O
Notes
C C C
O
O
W mA
Caution : Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to "ABSOLUTE MAXIMUM RATINGS" conditions for extended periods may affect device reliability.
Recommended DC,AC Operating Conditions (Notes : 1)
Symbol VDD VDDQ VREF V IH ( D C ) V IL ( D C ) V ICK ( D C ) V ID ( D C ) V IH ( A C ) V IL ( A C ) V ID ( A C ) VX (AC) V ISO ( A C ) Power Supply Voltage Power Supply Voltage (for I/O Buffer) Input Reference Voltage Input DC high Voltage Input DC Low Voltage Differential Clock DC Input Voltage Input Differential Voltage. CLK and C L K Inputs (DC) Input AC High Voltage Input AC Low Voltage Input Differential Voltage. CLK and C L K Inputs (AC) Differential AC Input Cross Point Voltage Differential Clock AC Middle Level Parameter Min 2.375 1.7 V DDQ / 2 x 9 6 % V R E F+ 0 . 1 2 5 -0.1 -0.1 0.4 V R E F+ 0 . 2 -0.1 0.55 V DDQ / 2 - 0 . 1 2 5 V DDQ / 2 - 0 . 1 2 5 Typ 2.5 1.8
(Ta = 0 ~ 70
O
C) Units V V V V V V V V V V V V 2 5 5 10 7,10 3,6 4,6 7,10 8,10 9,10 Notes
Max 2.625 1.9 V DDQ / 2 x 1 0 5 % V DDQ +0.2 V R E F- 0 . 1 2 5 V DDQ +0.1 V DDQ +0.2 V DDQ +0.2 V REF-0.2 V DDQ +0.2 V DDQ /2+0.125 V DDQ /2+0.125
V D D Q /2 -
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K4C89363AF
Notes: 1. All voltages are referenced to Vss, VssQ. 2. V REF i s e x p e c t e d t o t r a c k v a r i a t i o n s i n V d d Q D C l e v e l o f t h e t r a n s m i t t i n g d e v i c e . P e a k t o p e a k A C n o i s e o n V REF m a y n o t e x c e e d 2 % o f V R E F ( D C ) . 3. Overshoot Iimit : V IH( m a x . ) = V d d Q + 0 . 7 V w i t h a p u l s e w i d t h < = 5 n s 4 . U n d e r s h o o t I i m i t : V I L( m i n . ) = - 0 . 7 V w i t h a p u l s e w i d t h < = 5 n s 5 . V I H ( D C ) a n d V IL ( D C ) a r e l e v e l s t o m a i n t a i n t h e c u r r e n t l o g i c s t a t e . 6 . V I H ( A C ) a n d V I L( A C ) a r e l e v e l s t o c h a n g e t o t h e n e w l o g i c s t a t e . 7. V ID i s m a g n i t u d e o f t h e d i f f e r e n c e b e t w e e n C L K i n p u t l e v e l a n d C L K input level. 8. The value of Vx(AC) is expected to equal VddQ/2 of the transmitting device. 9 . V I S O m e a n s [ V I C K( C L K ) + V I C K (C L K ) ] / 2 10. Refer to the figure below.
CLK
VX VX VX VX VX V ID ( A C )
CLK
VI C K V ICK VI C K VI C K
VSS V ID ( A C )
0 V Differential V ISO
V ISO(min) V I S O (max)
VSS 1 1 . I n t h e c a s e o f e x t e r n a l t e r m i n a t i o n , V T T ( T e r m i n a t i o n V o l t a g e ) s h o u l d b e g o n e i n t h e r a n g e o f V R E F( D C ) 0 . 0 4 V .
Pin Capacitance
Symbol C IN C INC C I/O C NC
(V DD = 2 . 5 V , V D D Q = 1 . 8 V , f = 1 M H z , T a = 2 5 C )
Parameter Min 1.5 1.5 2.5 Max 2.5 2.5 3.5 1.5 Delts 0.25 0.25 0.5 Units pF pF pF pF
o
Input Pin Capacitance Clock Pin (CLK, C L K ) Capacitance DQ, DS, QS Capacitance NC Pin Capacitance
Note : These parameters are periodically sampled and not 100% tested.
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K4C89363AF
DC Characteristics and Operating Conditions
Parameter Symbol F6
Operating Current t CK = m i n , I RC = m i n Read/Write command cycling O V < = V IN< = V IL(AC) ( m a x . ) V IH(AC) ( m i n . ) < = VIN < = V DDQ 1 bank operation, Burst Length = 4 A d d r e s s c h a n g e u p t o 2 t i m e s d u r i n g m i n i m u m IR C . Standby Current t CK = m i n , C S = V IH, P D = V IH , 0 V < = V IN< = V IL(AC) ( m a x . ) V IH(AC) ( m i n . ) < = V IH < = VDDQ All Banks : inactive state O t h e r i n p u t s i g n a l s a r e c h a n g e d o n e t i m e d u r i n g 4 * tC K Standby (Power Down) Current t CK = m i n , C S = V IH, P D = V IL ( P o w e r D o w n ) 0 V < = V IN< = V DDQ All Banks : inactive state Auto-Refresh Current t CK = m i n , I REFC = m i n , t REFI = m i n Auto-Refresh command cycling 0 V < = V IN< = V IL( A C ) ( m a x . ) , V IH( A C ) ( m i n . ) < = V IN < = V DDQ A d d r e s s c h a n g e u p t o 2 t i m e s d u r i n g m i n i m u m I R E F C. Self-Refresh Current self-Refresh mode P D = 0 . 2 V , O V < = V IN < = V DDQ I DD6 TBD TBD TBD I DD5 TBD TBD TBD 1 I DD2P TBD TBD TBD mA 1 ID D 2 N TBD TBD TBD 1 I DD1S TBD TBD TBD 1, 2
(Vdd = 2.5V 0.125V, VddQ = 1.8V 0.1V, Ta = 0~70 C ) Max Units FB F5 Notes
Parameter
Input Leakage Current ( 0 V < = V IN< = V d d Q , A l l o t h e r p i n s n o t u n d e r t e s t = 0 V ) Output Leakage Current ( O u t p u t d i s a b l e d , 0 V < = VO U T < = V d d Q ) V REF C u r r e n t Output Source DC Current V d d Q = 1 . 7 V / V OH = 1 . 4 2 0 V Normal Output Driver Output Sink DC Current V d d Q = 1 . 7 V / V OL = 0 . 2 8 0 V Output Source DC Current V d d Q = 1 . 7 V / V OH = 1 . 4 2 0 V Strong Output Driver Output Sink DC Current V d d Q = 1 . 7 V / V OL = 0 . 2 8 0 V Output Source DC Current V d d Q = 1 . 7 V / V OH = 1 . 4 2 0 V Weak Output Driver Output Sink DC Current V d d Q = 1 . 7 V / V OL = 0 . 2 8 0 V
Symbol
ILI
Min
-5
Max
5
Unit
uA
Notes
I LO I REF I O H( D C )
-5
5
uA
-5
5
uA
-5.6
-
3
IOL ( D C )
5.6
-
3
I O H( D C )
-9.8
mA
3
IOL ( D C )
9.8
-
3
I O H( D C )
-2.8
-
3
IOL ( D C )
2.8
-
3
N o t e s : 1 . T h e s e p a r a m e t e r s d e p e n d o n t h e c y c l e r a t e a n d t h e s e v a l u e s a r e m e a s u r e d a t a c y c l e r a t e w i t h t h e m i n i m u m v a l u e s o f t C K, t RC a n d I RC . 2. These parameters depend on the output loading. The specified values are obtained with the output open. 3. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Regis ter.
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K4C89363AF
AC Characteristics and Operating Conditions (Notes : 1, 2)
F6 Symbol Parameter Min
t RC Random Cycle Time CL = 4 t CK Clock Cycle Time CL = 5 CL = 6 t RAC t CH t CL t CKQS tQSQ t AC t OH t HP t QSP t QSQV t QHS t DQSS t DSPRE t DSPRES t DSPREH t DSP Random Access Time Clock High Time Clock Low Time QS Access Time from CLK Data Output Skew from QS Data Access Time from CLK Data Output Hold Time from CLK C L K h a l f p e r i o d ( m i n i u m o f A c t u a l tC H , t CL ) QS(Read) Pulse Width Data Output Valid Time from QS 20.0 4.0 3.33 3.0 0 . 4 5 * tC K 0 . 4 5 * tC K -0.45 -0.5 -0.5 m i n ( tC H , t CL ) t HP-t QHS t HP-t QHS 0.8*t C K 0.4*t C K 0 0.3*t C K 0 . 4 5 * tC K CL = 4 t DSS DS Input Falling Edge to Clock Setup Time CL = 5 CL = 6 t DSPST DS(Write) Postamble Pulse Width CL = 4 t DSPSTH DS(Write) Postamble Hold Time CL = 5 CL = 6 t DS t DH t IS t IH Data Input Setup Time from DS Data Input Hold Time from DS Command / Address Input Setup Time Command / Address Input Hold Time 0.9 0.9 0.9 0 . 4 5 * tC K 0.9 0.9 0.9 0.3 0.3 0.6 0.6
FB Max
7.5 7.5 7.5 20.0 0.45 0.2 0.5 0.5 0.055x t CK+ 0 . 1 7 1.2*t C K 0.55*t C K -
F5 Units Notes Max
7.5 7.5 7.5 22.5 0.45 0.25 0.5 0.5 0.055x tC K+0.17 1.2*t C K 0.55*t C K -
Min
22.5 4.5 3.75 3.33 0.45*tC K 0.45*tC K -0.45 -0.5 -0.5 min(tC H , tC L ) t H P-tQ H S t H P-tQ H S 0 . 8 * tC K 0 . 4 * tC K 0 0 . 3 * tC K 0.45*tC K 0.9 0.9 0.9 0.45*tC K 0.9 0.9 0.9 0.35 0.35 0.6 0.6
Min
25 5.0 4.5 4.0 0 . 4 5 * tC K 0 . 4 5 * tC K -0.5 -0.6 -0.6 m i n ( tC H , t CL ) t HP-t QHS t HP-t QHS 0.8*t C K 0.4*t C K 0 0.3*t C K 0 . 4 5 * tC K 1.0 1.0 1.0 0 . 4 5 * tC K
Max
7.5 7.5 7.5 25 0.5 0.3 0.6 0.6 0.055x t CK+ 0 . 1 7 1.2*t C K 0.55*t C K ns 3 4 3 3 4 3, 4 3, 4 3, 4 4 3, 4 3, 4 3, 4 4 4 3 3 3 3 3 3 3 3 3 3, 8 4 3, 8 3, 8 3 4, 8 4, 8
DQ, QS Hold skew factor
DS(Write) Low to High Setup Time DS(Write) Preamble Pulse Width DS First Input Setup Time DS First Low Input Hold Time DS High or Low Input Pulse Width
-
1.0 1.0 1.0 0.4 0.4 0.7 0.7
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K4C89363AF
AC Characteristics and Operating Conditions (Notes : 1, 2) (Continued)
F6 Symbol
tL Z tH Z tQPDH tPDEX tT tF P D L tR E F I tPAUSE
FB Max
0.5 1 5 3.9 1 2 -
F5 Units Notes Max
0.5 1 5 3.9 1 2 -
Parameter Min
Data-out Low Impedance Time from CLK Data-out High Impedance Time from CLK Last Output to P D H i g h H o l d T i m e Power Down Exit Time Input Transition Time P D Low Input Window for Self-Refresh Entry Auto-Refresh Average Interval Pause Time after Power-up CL = 4 Random Read/Write Cycle Time -0.5 0 0.6 0.1 -0.5*t C K 0.4 200 5 6 7 1 CL = 4 4 5 6 2 BL = 2 BL = 4 2 3 1 CL = 4 7 7 7 1 CL = 4 19 23 25 19 23 25 I REFC 200
Min
-0.5 0 0.6 0.1 - 0 . 5 * tC K 0.4 200 5 6 7 1 4 5 6 2 2 3 1 7 7 7 1 19 23 25 19 23 25 I REFC 200
Min
-0.6 0 0.7 0.1 -0.5*t C K 0.4 200 5 6 7 1 4 5 6 2 2 3 1 7 7 7 1 19 23 25 19 23 25 IREFC 200
Max
0.6 1 5 3.9 us 1 2 3 5 3 3, 6, 8 3, 7, 8
IR C
CL = 5 (Applicable to Same Bank) CL = 6
IRCD
RDA/WRA to LAL Command Input Delay (Applicable to Same Bank)
IRAS
LAL to RDA/WRA Command Input Delay (Applicable to Same Bank)
CL = 5 CL = 6
IRBD
Random Bank Access Delay (Applicable to Other Bank) LAL following RDA to WRA Delay (Applicable to Other Bank) LAL following WRA to RDA Delay (Applicable to Other Bank)
IRWD
IWRD
Cycle
IRSC
Mode Register Set Cycle Time
CL = 5 CL = 6
IPD IP D A
P D Low to Inactive State of Input Buffer P D High to Active State of Input Buffer
IP D V
Power down mode valid from REF command
CL = 5 CL = 6 CL = 4
IR E F C
Auto-Refresh Cycle Time
CL = 5 CL = 6
ICKD ILOCK
REF Command to Clock Input Disable at Self-Refresh Entry DLL Lock-on Time (Applicable to RDA command)
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K4C89363AF
AC Test Conditions
Symbol V IH ( m i n ) V IL ( m a x ) V REF V TT V SWING VR V ID ( A C ) SLEW V OTR Parameter Input high voltage (minimum) Input low voltage (maximum) Input reference voltage Termination voltage Input signal peak to peak swing Differential clock input reference level Input differential voltage Input signal minimum slew rate Output timing measurement reference voltage Value V REF + 0.2 V REF - 0.2 VddQ/2 VREF 0.7 V X(AC) 1.0 2.5 VddQ/2 Units V V V V V V V V/ns V V TT 50 9 Notes
VddQ
V IH min (AC) V SWING VREF Output V IL m a x (AC) 25
Z=50
Z=50
Vss T T
50 V TT
S l e w = ( V I H m i n ( A C ) - V I L m a x ( A C ) ) / T
AC Test Load
N o t e s : 1 . T r a n s i t i o n t i m e s a r e m e a s u r e d b e t w e e n V I H m i n ( D C ) a n d V IL m a x ( D C ) . Transition (rise and fall) of input signals have a fixed slope. 2. If the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., tD Q S S = 0 . 8 * t C K , tC K = 3 . 3 n s , 0 . 8 * 3 . 3 n s = 2 . 6 4 n s i s r o u n d e d u p t o 2 . 7 n s . ) 3. These parameters are measured from the differential clock (CLK and C LK) AC cross point. 4 . T h e s e p a r a m e t e r s a r e m e a s u r e d f r o m s i g n a l t r a n s i t i o n p o i n t o f D S c r o s s i n g V R E F level. 5. The t REFI(MAX.) applies to equally distributed refresh method. The t REFI(MIN.) applies to both burst refresh method and distributed refresh method. In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400ns always. In other words, the number of Auto- Refresh cycles which can be performed within 3.2us (8X400ns) is to 8 times in the maximum. 6. Low Impedance State is speified at VddQ/2 0.2V from steady state. 7. High Impedance State is specified where output buffer is no longer driven. 8. These parameters depend on the clock jitter. These parameters are measured at stable clock. 9. Output timing is measured by using Normal driver strength.
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Power Up Sequence
1. As for PD , being maintained by the low state (<0.2V) is desirable before a power-supply injection. 2 . A p p l y V DD b e f o r e o r a t t h e s a m e t i m e a s V DDQ . 3 . A p p l y V D D Q b e f o r e o r a t t h e s a m e t i m e a s V R E F. 4. Start clock (CLK, C L K ) and maintain stable condition for 200us (min.). 5. After stable power and clock, apply DESL and take PD = H. 6. Issue EMRS to enable DLL and to define driver strength and data strobe type. (Note : 1) 7. Issue MRS for set C A S Latency (CL), Burst Type (BT), and Burst Length (BL). (Note : 1) 8. Issue two or more Auto-Refresh commands. (Note:1) 9. Ready for normal operation after 200 clocks from Extended Mode Register programming.
Note : 1. Sequence 6, 7 and 8 can be issued in random order. 2. L=Logic Low, H = Logic High
2.5V(TYP)

V DD
1.8V(TYP)

V DDQ
0.9V(TYP)

V REF
CLK CLK
200 s(min) PD

tP D E X IP D A lR S C

lR S C
lR E F C

lR E F C

200 clock cycle(min)

Command
DESL
RDA MRS
DESL
RDA MRS
DESL
WRA REF
DESL
WRA REF
DESL
op-code
op-code

Address
EMRS
MRS

DQ

DS
Hi-Z QS (Uni-QS mode)

Low
QS (Free Running mode)
EMRS
MRS
Auto Refresh cycle
Normal Operation
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Basic Timing Diagrams
Input Timing
Command and Address
tC K tC K tC H tC L
CK
~
CK
tI S tIH tI S tIH
~~ ~
CS
1st tIPW tI S tIH tI S
2nd
tIH
~~ ~~
FN
1st
2nd tI P W
tI S
tIH
tI S
tIH
~~ ~~
A0-A14 BA0.BA1
UA, BA
LA
~
Data
LDS/UDS
tD S tD H tD S tD H
~~ ~
DQn (Input)
tD S t DH tD S tD H
~~ ~
DQm (Input)
Refer to the Command Truth Table.
Timing of the CLK, C L K
tC H
tC L
CLK
V IH V IH(AC) V IL(AC) tT tC K tT V IL
CLK
CLK
V IH V ID(AC)
CLK
VX
VX
VX
V IL
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Read Timing (Burst Length = 4)
Unidirectional DS/QS mode
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
tC H
tC L
tC K
CK CK
tI S tIH
Input (Control & Addresses)
L A L( a f t e r R D A ) DESL
LDS/UDS (Input)
tC K Q S tC K Q S tQSP tQ S P
C A S latency = 4 LQS/UQS (Output)
Low
tCKQS
Low tQSQV tQ S Q tQSQ tQ S Q V tQSQ t HZ Q3
t LZ
DQ (Output)
High-Z Q0 tA C Q1 tA C Q2 tA C
tOH
tC K Q S
tC K Q S tQSP tQSP
C A S latency = 5 LQS/UQS (Output)
Low
tC K Q S
Low tQ S Q V tQ S Q tQSQ tQ S Q V tQSQ tHZ Q3
tL Z
DQ (Output)
High-Z Q0 tA C Q1 tA C Q2 tA C
tOH
tC K Q S
tCKQS tQ S P tQ S P
C A S latency = 6 LQS/UQS (Output)
Low
tC K Q S
Low tQ S Q V tQSQ tQ S Q tQ S Q V tQ S Q tH Z Q3
tL Z
DQ (Output)
High-Z Q0 t AC Q1 tA C Q2 t AC
tO H
Note : DQ0 to DQ17 are aligned with LQS. DQ18 to DQ35 are aligned with UQS.
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Read Timing (Burst Length = 4)
Unidirectional DS/Free Running QS mode
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
tC H
tC L
tC K
CK CK
tI S tIH
Input (Control & Addresses)
L A L( a f t e r R D A ) DESL
LDS/UDS (Input)
tC K Q S tC K Q S tQSP tQ S P
C A S latency = 4 LQS/UQS (Output)
t LZ
tCKQS
tQSQV tQ S Q tQSQ tQ S Q V
tQSQ t HZ Q3
DQ (Output)
High-Z Q0 tA C Q1 tA C Q2 tA C
tOH
tC K Q S
tC K Q S tQSP tQSP
C A S latency = 5 LQS/UQS (Output)
tL Z
tC K Q S
tQ S Q V tQ S Q tQSQ tQ S Q V
tQSQ tHZ Q3
DQ (Output)
High-Z Q0 tA C Q1 tA C Q2 tA C
tOH
tC K Q S
tCKQS tQ S P tQ S P
C A S latency = 6 LQS/UQS (Output)
tL Z
tC K Q S
tQ S Q V tQSQ tQ S Q tQ S Q V
tQ S Q tH Z Q3
DQ (Output)
High-Z Q0 t AC Q1 tA C Q2 t AC
tO H
Note : DQ0 to DQ17 are aligned with LQS. DQ18 to DQ35 are aligned with UQS. LQS/UQS is always asserted in Free Running QS mode.
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K4C89363AF
Write Timing (Burst Length = 4)
Unidirectional DS/QS mode, Unidirectional DS/Free Running QS mode
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
tC H
tC L
tC K
CK CK
tI S tIH
Input (Control & Addresses)
L A L( a f t e r R D A ) DESL tDQSS tD S P R E S tD S P tD S P tD S P tDSPSTH tD S S tDSPREH tD S P S T
C A S latency = 4 LDS/UDS (Input)
Preamble tD S P R E tD H tD S
tD S S tD S tD S t DH Q0 Q1 Q2
Postamble
tD H Q3
DQ (Input)
tD Q S S tD S P R E S tDSS tDSPREH tD S P tD S P tD S P
tD S S tD S P S T H tDSPST
C A S latency = 5 LDS/UDS (Input)
Preamble
tD S P R E tD S tD H
Postamble tD S t DH t DS tD H Q3
DQ (Input)
Q0
Q1
Q2
tDQSS tD S P R E S tD S S tDSPREH tD S P tD S P tD S P
tD S S tD S P S T H tDSPST
C A S latency = 6 LDS/UDS (Input)
Preamble tDSPRE tD H
Postamble tD S tD S t DH Q1 Q2 t DS tD H Q3
DQ (Input)
Q0
LQS/UQS (Uni-QS)
Low
LQS/UQS (Free Runninig)
Note : DQ0 to DQ17 are sampled at both edges of LDS. DQ18 to DQ35 are sampled at both edges of UDS.
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t R E F I, t P A U S E, I x x x x T i m i n g
CLK CLK
tI S tIH
tR E F I , tP A U S E , IX X X X
~ ~
t IS
t IH
Input (Control & Addresses)
Command
~ ~
Command
N o t e . " I X X X X " m e a n s " IR C " ,
"I R C D " ,
" IR A S " , e t c .
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K4C89363AF
Function Truth Table (Notes : 1,2,3)
Command Truth Table (Notes : 4)
*T h e F i r s t C o m m a n d Symbol DESL RDA WRA Function Device Deselect Read with Auto-close Write with Auto-close CS H L L FN X H L BA1-BA0 X BA BA A14-A9 X UA UA A8 X UA UA A7 X UA UA A6-A0 X UA UA
*T h e S e c o n d C o m m a n d ( T h e n e x t c l o c k o f R D A o r W R A c o m m a n d ) Symbol LAL REF MRS Function Lower Address Latch Auto-Refresh Mode Register Set CS H L L FN X X X BA1-BA0 X X V A14-A13 V X L A12-A11 X X L A10-A9 X X L A8 X X L A7 X X V A6-A0 LA X V
Notes : 1 . L = L o g i c L o w , H = L o g i c H i g h , X = e i t h e r L o r H , V = V a l i d ( S p e c i f i e d V a l u e ) , B A = B a n k A d d r e s s , U A = U p p e r A d d r e s s , LA = Lower Address. 2. All commands are assumed to issue at a valid state. 3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input where CLK goes to High. 4. Operation mode is decided by the comination of 1st command and 2nd command refer to "STATE DIAGRAM" and the command table below.
Read Command Table
Command (Symbol) RDA (1st) LAL (2nd) CS L H FN H X BA1-BA0 BA X A14-A9 UA X A8 UA X A7 UA X A6-A0 UA LA Notes
Write Command Table
Command (Symbol) WRA (1st) LAL (2nd) CS L H FN L X BA1BA0 BA X A14 UA VW0 A13 UA VW1 A12 UA X A11 UA X A10~ A9 UA X A8 UA X A7 UA X A6-A0 UA LA
Notes : 5. A14~A13 are used for Variable Write Length (VW) control at Write Operation.
VW Truth Table
Function Write All Words BL = 2 Write First One Word Reserved Write All Words BL = 4 Write First Two Words Write First One Word L H H H H L H X L L VW0 L VW1 X
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Function Truth Table (Continued)
Mode Register Set Command Truth Table
Command (Symbol) RDA (1st) MRS (2nd) CS L L FN H X BA1-BA0 X V A14-A9 X L A8 X L A7 X V A6-A0 X V 6 Notes
Note : 6. Refer to "Mode Register Table".
Auto-Refresh Command Table
Command (Symbol) Current State n-1 H H PD CS n H H L L L X X X X X X X X X X X FN BA1-BA0 A14-A9 A8 A7 A6-A0 Notes
Function
Active Auto-Refresh
WRA(1st) REF(2nd)
Standby Active
Self-Refresh Command Table
Command (Symbol) Current State PD CS n-1 H H L L n H L L H L L X H L X X X FN BA1BA0
Function
A14-A9
A8
A7
A6-A0
Notes
Active Self-Refresh Entry Self-Refresh Continue Self-Refresh Exit
WRA(1st) REF(2nd) SELFX
Standby Active Self-Refresh Self-Refresh
X X X X
X X X X
X X X X
X X X X
X X X X 9 7, 8
Power Down Table
Command (Symbol) Current State PD CS n-1 H L L n L L H H X H X X X FN BA1BA0
Function
A14-A9
A8
A7
A6-A0
Notes
Power Down Entry Power Down Continue Power Down Exit Notes :
PDEN PDEX
Standby Power Down Power Down
X X X
X X X
X X X
X X X
X X X
8
9
7. PD has to be brought to Low within t FPDL f r o m R E F c o m m a n d . 8. P D should be brought to Low after DQ's state turned high impedance. 9 . W h e n PD is brought to High from Low, this function is executed asynchronously.
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Function Truth Table (Continued)
PD Current State n-1 H H H Idle H H L H H Row Active for Read H H L H H Row Active for Write H H L H H H Read H H L H H H Write H H L H H Auto-Refreshing H H H L H H Mode Register Accessing H H H L H L Power Down L L H L Se;f-Refreshing L L Notes : 10. Illegal if any bank is not idle. 11. Illegal to bank in specified states : Function may be Legal in the bank indicated by bank Address (BA). 1 2 . I l l e g a l i f t FPDL i s n o t S t i s f i e d . H H H L X X X X SELFX E x i t S e l f - R e f r e s h - > I d l e a f t e r I REFC Illegal L L X H H H L L X H H H L L X X L H H X L H L X H L L H L X H L L H L X X X H L X X X X X X H L X X X X H L X X X X X X X X X X X X X BA, UA BA, UA X X X X BA, UA BA, UA X X X X X X X X X PDEN DESL RDA WRA PDEN DESL RDA WRA PDEN RDEX Illegal Illegal Invalid N O P - > I d l e a f t e r I REFC Illegal Illegal Self-Refresh entry Illegal Refer to Self-Refreshing state N o p - > I d l e a f t e r IRSC Illegal Illegal Illegal Illegal Invalid Invalid Maintain Power Down Mode E x i t P o w e r D o w n M o d e - > I d l e a f t e r t PDEX Illegal Invalid Maintain Self-Refresh 12 L L X H H H H L X H L L X X X X H L X X X X BA, UA BA, UA PDEN DESL RDA WRA Illegal Illegal Invalid Data write & continue burst write to end Illegal Illegal 11 11 L L X H H L L X H H L L X H H H H L X H L H L X H L H L X H L L X X X X X X X X X X X X X X H L X X X LA Op-Code X X X LA X X X X X BA, UA BA, UA PDEN LAL MRS/EMRS PDEN MRS/EMRS LAL REF PDEN REF (Self) DESL RDA WRA Power Down Entry Illegal Refer to Power Down state Begin read Access to Mode Register Illegal Illegal Invalid Begin Write Auto-Refresh Illegal Self-Refresh entry Invalid Continue burst read to end Illegal Illegal 11 11 10 n H H H H L L X H L X BA, UA BA, UA DESL RDA WRA NOP Row activate for Read Row activate for Write CS FN Address Command Action Notes
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K4C89363AF
Mode Register Table
Regular Mode Register (Notes : 1)
Address Register B A 1 *1 0 B A 0 *1 0 A14-A8 0 A 7 *3 TM A6-A4 CL A3 BT A2-A0 BL
A7 0 1
Test Mode (TM) Regular (Default) Test Mode Entry
A3 0 1
Burst Type (BT) Sequential Interleave
A6 0 0 0 1 1 1 1
A5 0 1 1 0 0 1 1
A4 X 0 1 0 1 0 1
C A S Latency (CL) Reserved *2 Reserved
*2
A2 0 0 0 0 1
A1 0 0 1 1 X
A0 0 1 0 1
Burst Length (BL) Reserved *2 2 4
Reserved *2 4 5 6 Reserved *2
Reserved *2 X
Extended Mode Register (Notes : 4)
Address Register B A 1 *4 0 B A 0 *4 1 A14-A7 0 A6~A5 SS A4-A3 DIC(QS) A2~A1 DIC(DQ) A 0 *5 DS
A6 0 0 1 1
A5 0 1 0 1
Strobe Select Reserved
*2
QS A4 0 0 1 1 A3 0 1 0 1 A2 0 0 1 1
DQ A1 0 1 0 1
Output Driver Impedance Control (DIC) Normal Output Driver Strong Output Driver Weak Output Driver Reserved
Reserved*2 Unidirectional DS/QS Unidirectional DS/Free Running QS
Note : 1. Regular Mode Register Is Chosen Using the combination of BA0 = 0 and BA1 = 0. 2. "Reserved" places in Regular Mode Register should not be set. 3. A7 in Regular Mode Register must be set to "0"(Low state). Because Test Mode is specific mode for supplier. 4. Extended Mode Register is chosen using the Combination of BA0 = 1 and BA1 = 0. 5. A0 in Extended Mode Register must be set to "0" to enable DLL for normal operation.
A0 0 1
DLL Switch (DS) DLL Enable DLL Disable
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State Diagram
Self Refresh SELFX (PD = H ) Power Down
PDEX (P D = H ) PDEN
PD = L Standby (Idle)
(P D = L )
PD = H AutoRefresh WRA
Mode Register RDA
REF
MRS
Active (Restore)
Active
LAL
LAL
Write (Buffer)
Read
Command Input Automatic Return The second command at Active state must be issued 1clock after RDA or WRA command input
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K4C89363AF
Timing Diagrams
Single Bank Read Timing (CL=4)
0 CLK CLK l R C =5cycles l RC = 5 c y c l e s lR C = 5 c y c l e s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Command
RDA
LAL
DESL lR A S = 4 c y c l e s
RDA
LAL
DESL l R A S =4cycles
RDA
LAL
DESL l R A S= 4 c y c l e s
RDA
lR C D =1cycle Address UA LA
l R C D =1cycle UA LA
l R C D =1cycle UA LA
UA
Bank Add.
#0
#0
#0
#0
Unidirectional DS/QS mode BL =2 LDS/UDS (Input)
LQS/UQS (Output)
Low CL=4 CL=4 CL=4
DQ (Output)
Hi-Z Q0 Q1 Q0 Q1 Q0
BL =4 LDS/UDS (Input)
LQS/UQS (Output)
Low CL=4 CL=4 CL=4
DQ (Output)
Hi-Z Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0
Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input)
LQS/UQS (Output) CL=4 DQ (Output) Hi-Z Q0 Q1 Q0 Q1 Q0 CL=4 CL=4
BL =4 LDS/UDS (Input)
LQS/UQS (Output) CL=4 DQ (Output) Hi-Z Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 CL=4 CL=4
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Single Bank Read Timing (CL=5)
0 CLK CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
l R C =6cycles
l RC = 6 c y c l e s
Command
RDA
LAL
DESL l R A S= 5 c y c l e s
RDA
LAL
DESL lR A S= 5 c y c l e s
RDA lR C D =1cycle
LAL
DESL
l R C D =1cycle
l R C D =1cycle
Address
UA
LA
UA
LA
UA
LA
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode BL =2 LDS/UDS (Input)
LQS/UQS (Output)
Low CL=5 CL=5
DQ (Output)
Hi-Z Q0 Q1 Q0 Q1
BL =4 LDS/UDS (Input)
LQS/UQS (Output)
Low CL=5 CL=5
DQ (Output)
Hi-Z Q0 Q1 Q2 Q3 Q0 Q 1 Q2 Q3
Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input)
LQS/UQS (Output) CL=5 Hi-Z Q0 Q1 Q0 Q1 CL=5
DQ (Output)
BL =4 LDS/UDS (Input)
LQS/UQS (Output) CL=5 DQ (Output) Hi-Z Q0 Q1 Q2 Q3 Q0 Q 1 Q2 Q3 CL=5
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Single Bank Read Timing (CL=6)
0 CLK CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
lR C = 7 c y c l e s
l R C =7cycles
Command
RDA
LAL
DESL l R A S= 6 c y c l e s
RDA
LAL
DESL l R A S= 6 c y c l e s
RDA
LAL
l R C D =1cycle
l R C D =1cycle
l R C D =1cycle
Address
UA
LA
UA
LA
UA
LA
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode BL =2 LDS/UDS (Input)
LQS/UQS (Output)
Low CL=6 CL=6
DQ (Output)
Hi-Z Q0 Q1 Q0 Q1
BL =4 LDS/UDS (Input)
LQS/UQS (Output)
Low CL=6 CL=6
DQ (Output)
Hi-Z Q0 Q1 Q2 Q3 Q0 Q1 Q2
Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input)
LQS/UQS (Output) CL=6 DQ (Output) Hi-Z Q0 Q1 Q0 Q1 CL=6
BL =4 LDS/UDS (Input)
LQS/UQS (Output) CL=6 DQ (Output) Hi-Z Q0 Q1 Q2 Q3 Q0 Q1 Q2 CL=6
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Single Bank Write Timing (CL=4)
0 CLK CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
l R C =5cycles
l RC = 5 c y c l e s
lR C = 5 c y c l e s
Command
WRA
LAL
DESL lR A S = 4 c y c l e s
WRA
LAL
DESL l R A S =4cycles
WRA
LAL
DESL l R A S= 4 c y c l e s
WRA
lR C D =1cycle Address UA LA
l R C D =1cycle UA LA
l R C D =1cycle UA LA
UA
Bank Add.
#0
#0
#0
#0
Unidirectional DS/QS mode BL =2 LDS/UDS (Input)
LQS/UQS (Output)
Low WL=3 WL=3 WL=3
DQ (Output)
D0
D1
D0
D1
D0
D1
BL =4 LDS/UDS (Input)
LQS/UQS (Output)
Low WL=3 WL=3 WL=3
DQ (Output) Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input)
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
LQS/UQS (Output) WL=3 DQ (Output) WL=3 WL=3
D0
D1
D0
D1
D0
D1
BL =4 LDS/UDS (Input)
LQS/UQS (Output) WL=3 DQ (Output) WL=3 WL=3
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
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Single Bank Write Timing (CL=5)
0 CLK CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
lR C = 6 c y c l e s
l R C =6cycles
Command
WRA
LAL
DESL l R A S= 5 c y c l e s
WRA
LAL
DESL lR A S = 5 c y c l e s
WRA
LAL
DESL
lR C D =1cycle Address UA LA
l R C D =1cycle UA LA
l R C D =1cycle UA LA
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode BL =2 LDS/UDS (Input)
LQS/UQS (Output)
Low WL=4 WL=4
DQ (Output)
D 0 D1
D0
D1
BL =4 LDS/UDS (Input)
LQS/UQS (Output)
Low WL=4 WL=4
DQ (Output) Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input)
D0
D1
D2
D3
D0
D1
D2
D3
LQS/UQS (Output) WL=4 DQ (Output) WL=4
D 0 D1
D0
D1
BL =4 LDS/UDS (Input)
LQS/UQS (Output) WL=4 DQ (Output) WL=4
D0
D1
D2
D3
D0
D1
D2
D3
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Single Bank Write Timing (CL=6)
0 CLK CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
lR C = 7 c y c l e s WRA LAL DESL l R A S= 6 c y c l e s WRA LAL
l R C =7cycles DESL lR A S = 6 c y c l e s WRA LAL
Command
lR C D =1cycle Address UA LA
l R C D =1cycle UA LA
lR C D = 1 c y c l e UA LA
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode BL =2 LDS/UDS (Input)
LQS/UQS (Output)
Low WL=5 WL=5
DQ (Output)
D0
D1
D0
D1
BL =4 LDS/UDS (Input)
LQS/UQS (Output)
Low WL=5 WL=5
DQ (Output) Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input)
D0
D1
D2
D3
D0
D1
D2
D3
LQS/UQS (Output) WL=5 DQ (Output) WL=5
D0
D1
D0
D1
BL =4 LDS/UDS (Input)
LQS/UQS (Output) WL=5 DQ (Output) WL=5
D0
D1
D2
D3
D0
D1
D2
D3
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Single Bank Read-Write Timing (CL=4)
0 CLK CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
l R C =5cycles
l RC = 5 c y c l e s
lR C = 5 c y c l e s
Command
RDA
LAL
DESL
WRA
LAL
DESL
RDA
LAL
DESL
WRA
Address
UA
LA
UA
LA
UA
LA
UA
Bank Add.
#0
#0
#0
#0
Unidirectional DS/QS mode BL =2 LDS/UDS (Input)
LQS/UQS (Output)
Low CL=4 WL=3 CL=4
DQ (Output)
Hi-Z Q0 Q1 D 0 D1 Q0
BL =4 LDS/UDS (Input)
LQS/UQS (Output)
Low CL=4 WL=3 CL=4
DQ (Output)
Hi-Z Q0 Q1 Q2 Q3 D0 D1 D2 D3 Q0
Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input)
LQS/UQS (Output) CL=4 DQ (Output) Hi-Z Q0 Q1 D 0 D1 Q0 WL=3 CL=4
BL =4 LDS/UDS (Input)
LQS/UQS (Output) CL=4 DQ (Output) Hi-Z Q0 Q1 Q2 Q3 D0 D1 D2 D3 Q0 WL=3 CL=4
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Single Bank Read-Write Timing (CL=5)
0 CLK CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
lR C = 6 c y c l e s
l R C =6cycles
Command
RDA
LAL
DESL
WRA
LAL
DESL
RDA
LAL
DESL
Address
UA
LA
UA
LA
UA
LA
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode BL =2 LDS/UDS (Input)
LQS/UQS (Output)
Low CL=5 WL=4
DQ (Output)
Hi-Z Q0 Q1 D0 D1
BL =4 LDS/UDS (Input)
LQS/UQS (Output)
Low CL=5 WL=4
DQ (Output)
Hi-Z Q0 Q1 Q2 Q3 D0 D1 D2 D3
Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input)
LQS/UQS (Output) CL=5 DQ (Output) Hi-Z Q0 Q1 D0 D1 WL=4
BL =4 LDS/UDS (Input)
LQS/UQS (Output) CL=5 DQ (Output) Hi-Z Q0 Q1 Q2 Q3 D0 D1 D2 D3 WL=4
Read data
Write data
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K4C89363AF
Single Bank Read-Write Timing (CL=6)
0 CLK CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
lR C = 7 c y c l e s RDA LAL DESL WRA LAL
l R C =7cycles DESL RDA LAL
Command
Address
UA
LA
UA
LA
UA
LA
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode BL =2 LDS/UDS (Input)
LQS/UQS (Output)
Low CL=6 WL=5
DQ (Output)
Hi-Z Q0 Q1 D0 D1
BL =4 LDS/UDS (Input)
LQS/UQS (Output)
Low CL=6 WL=5
DQ (Output)
Hi-Z Q0 Q1 Q2 Q3 D0 D1 D2 D3
Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input)
LQS/UQS (Output) CL=6 DQ (Output) Hi-Z Q0 Q1 D0 D1 WL=5
BL =4 LDS/UDS (Input)
LQS/UQS (Output) CL=6 DQ (Output) Hi-Z Q0 Q1 Q2 Q3 D0 D1 D2 D3 WL=5
Read data
Write data
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Multiple Bank Read Timing (CL=4)
0 CLK CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
lR B D =2cycles RDA LAL RDA LAL DESL RDA
lR B D= 2 c y c l e s LAL RDA
lR B D = 2 c y c l e s LAL RDA
lR B D = 2 c y c l e s LAL RDA
lR B D= 2 c y c l e s LAL RDA LAL RDA
Command
Address
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank Add.
Bank "a"
Bank "b" l RC (Bank"a")=5cycles
Bank "a"
Bank "b"
Bank "c"
Bank "d"
Bank "a"
Bank "b"
l R C (Bank"a")=5cycles Unidirectional DS/QS mode BL =2 LDS/UDS (Input) Low LQS/UQS (Output) CL=4 DQ (Output) Hi-Z Q a 0 Qa1 Q b 0 Qb1 Qa0 Q a 1 Qb0 Q b 1 Qc0 Q c 1 CL=4
BL =4 LDS/UDS (Input) Low LQS/UQS (Output) CL=4 DQ (Output) Hi-Z Q a 0 Qa1 Q a 2 Qa3 Q b 0 Q b 1 Qb2 Q b 3 Qa0 Q a 1 Q a 2 Q a 3 Q b 0 Q b 1 Q b 2 Q b 3 Qc0 Q c 1 Qc2 CL=4
Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input)
LQS/UQS (Output) CL=4 DQ (Output) Hi-Z
CL=4
Q a 0 Qa1
Q b 0 Qb1
Qa0 Q a 1
Qb0 Q b 1
Qc0 Q c 1
BL =4 LDS/UDS (Input)
LQS/UQS (Output) CL=4 DQ (Output) Hi-Z
CL=4
Q a 0 Qa1 Q a 2 Qa3 Q b 0 Q b 1 Qb2 Q b 3
Qa0 Q a 1 Q a 2 Q a 3 Q b 0 Q b 1 Q b 2 Q b 3 Qc0 Q c 1 Qc2
Note : l R C to the same bank must be satisfied
- 32 -
REV. 0.0 Sep. 2002
K4C89363AF
Multiple Bank Read Timing (CL=5)
0 CLK CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
lR B D =2cycles RDA LAL RDA LAL DESL RDA
lR B D =2cycles LAL RDA
lR B D = 2 c y c l e s LAL RDA
lR B D = 2 c y c l e s LAL RDA
lR B D =2cycles LAL RDA LAL
Command
Address
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
Bank Add.
Bank "a"
Bank "b" lR C ( B a n k " a " ) = 6 c y c l e s
Bank "a"
Bank "b"
Bank "c"
Bank "d"
Bank "a"
lR C ( B a n k " a " ) = 6 c y c l e s Unidirectional DS/QS mode BL =2 LDS/UDS (Input) Low LQS/UQS (Output) CL=5 DQ (Output) Hi-Z Q a 0 Qa1 Qb0 Q b 1 Q a 0 Qa1 Qb0 Q b 1 CL=5
BL =4 LDS/UDS (Input) Low LQS/UQS (Output) CL=5 DQ (Output) Hi-Z Q a 0 Qa1 Q a 2 Q a 3 Qb0 Q b 1 Qb2 Q b 3 Q a 0 Q a 1 Q a 2 Q a 3 Qb0 Q b 1 Q b 2 CL=5
Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input)
LQS/UQS (Output) CL=5 DQ (Output) Hi-Z
CL=5
Q a 0 Qa1
Qb0 Q b 1
Q a 0 Qa1
Qb0 Q b 1
BL =4 LDS/UDS (Input)
LQS/UQS (Output) CL=5 DQ (Output) Hi-Z
CL=5
Q a 0 Qa1 Q a 2 Q a 3 Qb0 Q b 1 Qb2 Q b 3
Q a 0 Q a 1 Q a 2 Q a 3 Qb0 Q b 1 Q b 2
- 33 -
REV. 0.0 Sep. 2002
K4C89363AF
Multiple Bank Read Timing (CL=6)
0 CLK CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
lR B D =2cycles RDA LAL RDA LAL DESL RDA
lR B D= 2 c y c l e s LAL RDA
lR B D = 2 c y c l e s LAL RDA
lR B D = 2 c y c l e s LAL RDA
lR B D= 2 c y c l e s LAL RDA
Command
Address
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank Add.
Bank "a"
Bank "b" lR C ( B a n k " a " ) = 7 c y c l e s lR C ( B a n k " a " ) = 7 c y c l e s
Bank "a"
Bank "b"
Bank "c"
Bank "d"
Bank "a"
Unidirectional DS/QS mode BL =2 LDS/UDS (Input) Low LQS/UQS (Output) CL=6 DQ (Output) Hi-Z Q a 0 Qa1 Qb0 Q b 1 Q a 0 Qa1 CL=6
BL =4 LDS/UDS (Input) Low LQS/UQS (Output) CL=6 DQ (Output) Hi-Z Q a 0 Q a 1 Qa2 Q a 3 Qb0 Q b 1 Q b 2 Q b 3 Q a 0 Qa1 Q a 2 CL=6
Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input)
LQS/UQS (Output) CL=6 DQ (Output) Hi-Z
CL=6
Q a 0 Qa1
Qb0 Q b 1
Q a 0 Qa1
BL =4 LDS/UDS (Input)
LQS/UQS (Output) CL=6 DQ (Output) Hi-Z
CL=6
Q a 0 Q a 1 Qa2 Q a 3 Qb0 Q b 1 Q b 2 Q b 3
Q a 0 Qa1 Q a 2
- 34 -
REV. 0.0 Sep. 2002
K4C89363AF
Multiple Bank Write Timing (CL=4)
0 CLK CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
lR B D =2cycles WRA LAL WRA LAL DESL WRA
lR B D= 2 c y c l e s LAL WRA
lR B D = 2 c y c l e s LAL WRA
lR B D = 2 c y c l e s LAL WRA
lR B D= 2 c y c l e s LAL WRA LAL WRA
Command
Address
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank Add.
Bank "a"
Bank "b" l RC (Bank"a")=5cycles
Bank "a"
Bank "b"
Bank "c"
Bank "d"
Bank "a"
Bank "b"
l R C (Bank"b")=5cycles Unidirectional DS/QS mode BL =2 LDS/UDS (Input) Low LQS/UQS (Output) WL=3 DQ (Output) WL=3
D a 0 Da1
D b 0 Db1
Da0 Da1
Db0 Db1
Dc0 Dc1
Dd0 Dd1
BL =4 LDS/UDS (Input) Low LQS/UQS (Output) WL=3 DQ (Output) Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input) WL=3
D a 0 Da1 D a 2 D a 3 Db0 D b 1 Db2 D b 3
D a 0 D a 1 D a 2 Da3 D b 0 Db1 D b 2 Db3 Dc0 Dc1 Dc2 Dc3 D d 0 D d 1
LQS/UQS (Output) WL=3 DQ (Output)
WL=3
D a 0 Da1
D b 0 Db1
Da0 Da1
Db0 Db1
Dc0 Dc1
Dd0 Dd1
BL =4 LDS/UDS (Input)
LQS/UQS (Output) WL=3 DQ (Output)
WL=3
D a 0 Da1 D a 2 D a 3 Db0 D b 1 Db2 D b 3
D a 0 D a 1 D a 2 Da3 D b 0 Db1 D b 2 Db3 Dc0 Dc1 Dc2 Dc3 D d 0 D d 1
- 35 -
REV. 0.0 Sep. 2002
K4C89363AF
Multiple Bank Write Timing (CL=5)
0 CLK CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
lR B D =2cycles WRA LAL WRA LAL DESL WRA
lR B D =2cycles LAL WRA
lR B D = 2 c y c l e s LAL WRA
lR B D = 2 c y c l e s LAL WRA
lR B D =2cycles LAL WRA LAL
Command
Address
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
Bank Add.
Bank "a"
Bank "b" lR C ( B a n k " a " ) = 6 c y c l e s
Bank "a"
Bank "b"
Bank "c"
Bank "d"
Bank "a"
lR C ( B a n k " b " ) = 6 c y c l e s Unidirectional DS/QS mode BL =2 LDS/UDS (Input) Low LQS/UQS (Output) WL=4 DQ (Output) WL=4
D a 0 Da1
D b 0 Db1
Da0 Da1
Db0 Db1
Dc0 Dc1
BL =4 LDS/UDS (Input) Low LQS/UQS (Output) WL=4 DQ (Output) Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input) WL=4
D a 0 D a 1 Da2 D a 3 Db0 D b 1 D b 2 D b 3
D a 0 D a 1 D a 2 Da3 D b 0 Db1 D b 2 Db3 Dc0 Dc1
LQS/UQS (Output) WL=4 DQ (Output)
WL=4
D a 0 Da1
D b 0 Db1
Da0 Da1
Db0 Db1
Dc0 Dc1
BL =4 LDS/UDS (Input)
LQS/UQS (Output) WL=4 DQ (Output) N o t e : IR C t o t h e s a m e b a n k m u s t b e s a t i s f i e d .
WL=4
D a 0 D a 1 Da2 D a 3 Db0 D b 1 D b 2 D b 3
D a 0 D a 1 D a 2 Da3 D b 0 Db1 D b 2 Db3 Dc0 Dc1
- 36 -
REV. 0.0 Sep. 2002
K4C89363AF
Multiple Bank Write Timing (CL=6)
0 CLK CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
lR B D =2cycles WRA LAL WRA LAL DESL WRA
lR B D= 2 c y c l e s LAL WRA
lR B D = 2 c y c l e s LAL WRA
lR B D = 2 c y c l e s LAL WRA
lR B D= 2 c y c l e s LAL WRA
Command
Address
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank Add.
Bank "a"
Bank "b" lR C ( B a n k " a " ) = 7 c y c l e s lR C ( B a n k " a " ) = 7 c y c l e s
Bank "a"
Bank "b"
Bank "c"
Bank "d"
Bank "a"
Unidirectional DS/QS mode BL =2 LDS/UDS (Input) Low LQS/UQS (Output) WL=5 DQ (Output) WL=5
D a 0 Da1
D b 0 Db1
Da0 D a 1
Db0 Db1
BL =4 LDS/UDS (Input) Low LQS/UQS (Output) WL=5 DQ (Output) Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input) WL=5
D a 0 D a 1 Da2 D a 3 Db0 D b 1 D b 2 D b 3
D a 0 D a 1 D a 2 D a 3 D b 0 Db1
LQS/UQS (Output) WL=5 DQ (Output)
WL=5
D a 0 Da1
D b 0 Db1
Da0 D a 1
Db0 Db1
BL =4 LDS/UDS (Input)
LQS/UQS (Output) WL=5 DQ (Output) N o t e : IR C t o t h e s a m e b a n k m u s t b e s a t i s f i e d .
WL=5
D a 0 D a 1 Da2 D a 3 Db0 D b 1 D b 2 D b 3
D a 0 D a 1 D a 2 D a 3 D b 0 Db1
- 37 -
REV. 0.0 Sep. 2002
K4C89363AF
Multiple Bank Read-Write Timing (BL=2)
0 CLK CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
lR B D =2cycles WRA LAL RDA LAL DESL WRA LAL RDA LAL DESL WRA LAL RDA LAL DESL WRA
Command
Address
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank Add.
Bank "a"
Bank "b"
Bank "c" l R C (Bank"a")
Bank "d"
Bank "a"
Bank "b"
Bank "c"
l R C (Bank"a") Unidirectional DS/QS mode
CL =4 LDS/UDS (Input)
LQS/UQS (Output)
Low WL=3 CL=4 D a 0 Da1 Q b 0 Qb1 Dc0 Dc1 Q d 0 Qd1 Da0 Da1
DQ (Output) CL =5 LDS/UDS (Input)
Hi-Z
LQS/UQS (Output)
Low WL=4 CL=5 D a 0 Da1 Q b 0 Qb1 Dc0 Dc1 Q d 0 Qd1 Da0 Da1
DQ (Output) CL =6 LDS/UDS (Input)
Hi-Z
LQS/UQS (Output)
Low WL=5 Hi-Z CL=6 D a 0 Da1 Q b 0 Qb1 Dc0 Dc1 Q d 0 Qd1
DQ (Output)
Unidirectional DS/Free Running QS mode
CL =4 LDS/UDS (Input)
LQS/UQS (Output)
WL=3
DQ (Output) CL =5 LDS/UDS (Input)
CL=4 Da0 Qa1 Q b 0 Qb1 Dc0 Q c 1 Q d 0 Qd1 Da0 Da1
Hi-Z
LQS/UQS (Output)
WL=4 Hi-Z
DQ (Output) CL =6 LDS/UDS (Input)
CL=5 D a 0 Da1 Q b 0 Qb1 Dc0 Dc1 Q d 0 Qd1 Da0 Da1
LQS/UQS (Output)
WL=5 Hi-Z
DQ (Output)
CL=6 D a 0 Da1 Q b 0 Qb1 Dc0 Dc1 Q d 0 Qd1
N o t e : IR C t o t h e s a m e b a n k m u s t b e s a t i s f i e d .
- 38 -
REV. 0.0 Sep. 2002
K4C89363AF
Multiple Bank Read-Write Timing (BL=4)
0 CLK CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
lR B D =2cycles WRA LAL RDA LAL DESL lR W D = 3 c y c l e s LA UA Bank "c" l R C (Bank"a") l R C (Bank"a") Unidirectional DS/QS mode
CL =4 LDS/UDS (Input)
Command
WRA
LAL
RDA
LAL
DESL l R W D =3cycles
WRA
LAL
RDA
LAL
l W R D =1cycle Address Bank Add. UA Bank "a" LA UA Bank "b"
l W R D =1cycle LA UA Bank "d" LA
l W R D =1cycle UA Bank "a" LA UA Bank "b" LA
LQS/UQS (Output)
Low WL=3 CL=4 D a 0 Da1 D a 2 D a 3 Q b 0 Q b 1 Q b 2 Qb3 D a 0 Da1 D a 2 D a 3 Qb0 Q b 1 Qb2 Q b 3
DQ (Output) CL =5 LDS/UDS (Input)
Hi-Z
LQS/UQS (Output)
Low WL=4 CL=5 D a 0 Da1 D a 2 D a 3 Q b 0 Qb1 Q b 2 Qb3 Da0 Da1 Da2 Da3 Qb0 Q b 1 Qb2 Q b 3
DQ (Output) CL =6 LDS/UDS (Input)
Hi-Z
LQS/UQS (Output)
Low WL=5 CL=6 D a 0 Da1 D a 2 D a 3 Q b 0 Qb1 Q b 2 Qb3 Da0 Da1 Da2 Da3 Qb0 Q b 1
DQ (Output)
Hi-Z
Unidirectional DS/Free Running QS mode
CL =4 LDS/UDS (Input)
LQS/UQS (Output)
WL=3
DQ (Output) CL =5 LDS/UDS (Input)
CL=4 D a 0 Da1 D a 2 D a 3 Q b 0 Q b 1 Q b 2 Qb3 D a 0 Da1 D a 2 D a 3 Qb0 Q b 1 Qb2 Q b 3
Hi-Z
LQS/UQS (Output)
WL=4
DQ (Output) CL =6 LDS/UDS (Input)
CL=5 D a 0 Da1 D a 2 D a 3 Q b 0 Qb1 Q b 2 Qb3 Da0 Da1 Da2 Da3 Qb0 Q b 1 Qb2 Q b 3
Hi-Z
LQS/UQS (Output)
WL=5
DQ (Output)
CL=6 D a 0 Da1 D a 2 D a 3 Q b 0 Qb1 Q b 2 Qb3 Da0 Da1 Da2 Da3 Qb0 Q b 1
Hi-Z N o t e : IR C t o t h e s a m e b a n k m u s t b e s a t i s f i e d .
- 39 -
REV. 0.0 Sep. 2002
K4C89363AF
Write with Variable Write Length (VW) Control(CL=4)
0 CLK CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BL=2, SEQUENTIAL MODE Command WRA LAL DESL WRA LAL DESL
Address
UA
LA=#3 VW=All
UA
LA=#1 VW=1
VW0 = Low VW1 = don't care Bank Add. Bank "a" Bank "a"
VW0 = High VW1 = don't care
LDS/UDS (Input)
LQS/UQS (Input)
D0
D1
D0 #1 (#0) Last one data is masked.
Lower Address #3 #2
BL=4, SEQUENTIAL MODE Command WRA LAL DESL WRA LAL DESL WRA LAL DESL
Address
UA
LA=#3 VW=All
UA
LA=#1 VW=1
UA
LA=#2 VW=2
VW0 = High VW1 = Low Bank Add. Bank "a" Bank "a"
VW0 = High VW1 = High Bank "a"
VW0 = Low VW1 = High
LDS/UDS (Input)
LQS/UQS (Input) Lower Address
D0 #3
D1 #0
D2 #1
D3 #2
D0 #1 (#2) (#3) (#0) Last three data are masked.
D0 #2
D1 #3 (#0) (#1)
Last two data are masked.
Note : DS input must be continued till end of burst count even if some of laster data is masked.
- 40 -
REV. 0.0 Sep. 2002
K4C89363AF
Power Down Timing (CL=4, BL=4)
Read cycle to Power Down Mode
0 CLK CLK
1
2
3
4
5
6
7
8
9
10
n-1
n
n+1
n+2
n+3

BL=2, SEQUENTIAL MODE Command RDA LAL DESL

DESL IP D A
RDA or WRA
Address
UA
LA tI S I P D =2 cycle
UA
t IH PD tQ P D H Unidirectional DS/QS mode
IR C ( m i n ) , tR E F I ( m a x )

tPDEX

LDS/UDS (Input)
LQS/UQS (Output)
Low CL=4

DQ (Output)
Hi-Z Q0 Q1 Q2 Q3
Hi-Z

Unidirectional DS/Free Running QS mode

LDS/UDS (Input)

LQS/UQS (Output) CL=4 DQ (Output) Hi-Z Q0 Q1 Q2 Q3
Hi-Z

Power Down Entry
Power Down Exit
Note : P D must be kept "High" level until end of Burst data output. P D should be brought to "High" within tR E F I (max.) to maintain the data written into cell. In Power Down Mode, P D "Low" and a stable clock signal must be maintained. W h e n PD is brought to "High", a valid executable command may be applied I P D A cycles later.
- 41 -
REV. 0.0 Sep. 2002
K4C89363AF
Power Down Timing (CL=4, BL=4)
Write cycle to Power Down Mode
0 CLK CLK 1 2 3 4 5 6 7 8 9 10 n-1 n n+1 n+2 n+3

IP D A

Command
WRA
LAL
DESL
DESL
RDA or WRA

Address
UA
LA tI S I P D =2 cycle
UA
t IH PD

tPDEX WL=3 IP D =2 cycle IR C ( m i n ) , tR E F I ( m a x )
Unidirectional DS/QS mode

LDS/UDS (Input)
LQS/UQS (Output)
Low

WL=3

DQ (Output)
D0
D1
D2
D3
Unidirectional DS/Free Running QS mode

LDS/UDS (Input)

LQS/UQS (Output) WL=3

DQ (Output)
D0
D1
D2
D3
Note : P D must be kept "High" level until end of Burst data output. P D should be brought to "High" within tR E F I (max.) to maintain the data written into cell. In Power Down Mode, P D "Low" and a stable clock signal must be maintained. W h e n PD is brought to "High", a valid executable command may be applied I P D A cycles later.
- 42 -
REV. 0.0 Sep. 2002
K4C89363AF
Mode Register Set Timing (CL=4, BL=2)
From Read operation to Mode Register Set operation
0 CLK CLK l R C =7cycles RDA LAL DESL RDA MRS DESL RDA or WRA LAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Command
A14~A0
UA
LA
Valid (opcode)
UA
LA
BA0, BA1
BA CL + BL/2
BA0="0" BA1="0"
BA
Unidirectional DS/QS mode
LDS/UDS (Input)
LQS/UQS (Output)
Low
DQ (Output)
Q0
Q1
Unidirectional DS/Free Running QS mode
LDS/UDS (Input)
LQS/UQS (Output)
DQ (Output)
Q0
Q1
Note : Minimum delay from LAL following RDA to RDA of MRS operation is CL+BL/2.
- 43 -
REV. 0.0 Sep. 2002
K4C89363AF
Mode Register Set Timing (CL=4, BL=4)
From Write operation to Mode Register Set operation
0 CLK CLK l R C =7cycles WRA LAL DESL RDA MRS DESL RDA or WRA LAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Command
A14~A0
UA
LA
Valid (opcode)
UA
LA
BA0, BA1
BA WL + BL/2
BA0="0" BA1="0"
BA
Unidirectional DS/QS mode
LDS/UDS (Input)
LQS/UQS (Output)
Low
DQ (Output)
D0
D1
D2
D3
Unidirectional DS/Free Running QS mode
LDS/UDS (Input)
LQS/UQS (Output)
DQ (Output)
D0
D1
D2
D3
Note : Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/2.
- 44 -
REV. 0.0 Sep. 2002
K4C89363AF
Extended Mode Register Set Timing (CL=4, BL=2)
From Read operation to Extended Mode Register Set operation
0 CLK CLK l R C =7cycles RDA LAL DESL RDA MRS DESL RDA or WRA LAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Command
A14~A0
UA
LA
Valid (opcode)
UA
LA
BA0, BA1
BA CL + BL/2
BA0="0" BA1="0"
BA
Unidirectional DS/QS mode
LDS/UDS (Input)
LQS/UQS (Output)
Low
DQ (Output)
Q0
Q1
Unidirectional DS/Free Running QS mode
LDS/UDS (Input)
LQS/UQS (Output)
DQ (Output)
Q0
Q1
Note : M i n i m u m d e l a y f r o m L A L f o l l o w i n g R D A t o R D A o f E M R S o p e r a t i o n i s C L + B L / 2 . When DQ strobe mode is changed by EMRS, QS output is invalid for I R S C p e r i o d . DLL switch in Extended Mode Register must be set to enable mode for normal operation. DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.
- 45 -
REV. 0.0 Sep. 2002
K4C89363AF
Extended Mode Register Set Timing (CL=4, BL=4)
From Write operation to Extended Mode Register Set operation
0 CLK CLK l R C =7cycles WRA LAL DESL RDA MRS DESL RDA or WRA LAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Command
A14~A0
UA
LA
Valid (opcode)
UA
LA
BA0, BA1
BA WL + BL/2
BA0="0" BA1="0"
BA
Unidirectional DS/QS mode
LDS/UDS (Input)
LQS/UQS (Output)
Low
DQ (Output)
D0
D1
D2
D3
Unidirectional DS/Free Running QS mode
LDS/UDS (Input)
LQS/UQS (Output)
DQ (Output)
D0
D1
D2
D3
Note : When DQ strobe mode is changed by EMRS, QS output is invalid for I R S C p e r i o d . DLL switch in Extended Mode Register must be set to enable mode for normal operation. DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence. Minimum delay from LAL following WRA to RDA of EMRS operation is WL+BL/2.
- 46 -
REV. 0.0 Sep. 2002
K4C89363AF
Auto-Refresh Timing (CL=4, BL=4)
Unidirectional DS/QS mode 0 CLK CLK l R C =5cycles lR E F C = 1 9 c y c l e s 1 2 3 4 5 6 7 n-1 n n1 + n+2

Command
RDA
LAL
DESL
WRA
REF
DESL
RDA or WRA
LAL or MRS or REF

Bank, Address
Bank, UA
LA
l R C D =1cycle LQS/UQS (output) Low
l R A S= 4 c y c l e s
l R C D =1cycle Low

CL=4 DQ (output) Hi-Z Q0 Q1 Q2 Q3 Hi-Z

Unidirectional DS/Free Running QS mode CLK CLK l R C =5cycles lR E F C = 1 9 c y c l e s

Command
RDA
LAL
DESL
WRA
REF
DESL
RDA or WRA
LAL or MRS or REF

Bank, Address
Bank, UA
LA
lR C D = 1 c y c l e s LQS/UQS (output)
l R A S= 4 c y c l e s
l R C D =1cycles

CL=4 DQ (output) Hi-Z Q0 Q1 Q2 Q3 Hi-Z

Note : In case of CL=4, IR E F C must be meet 19 clock cycles. When the Auto-Refresh operation is perfomed, the synthetic average interval of Auto-Refresh command specified by tR E F I m u s t b e s a t i s f i e d . tR E F I is average interval time in 8 Refresh cycles that is sampled randomly.
t1
t2
t3
t7
t8

CLK W AR F R E
W ARF R E
W AR F R E
W AR F R E
W AR F R E
8 Refresh cycle t + t + t + t +t +t +t +t tR E F I = Total time of 8 Refresh cycle = 1 2 3 4 5 6 7 8 8 8 tR E F I is specified to avoid partly concentrated current of Refresh operation that is acivated larger are than Read/Write operation.
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K4C89363AF
Self-Refresh Entry Timing
Unidirectional DS/QS mode 0 CLK CLK lR C D = 1 c y c l e s lR E F C 1 2 3 4 5 6 7 8 9 10 11

Command
WRA tF P D L
REF tFPDL
DESL
(min)
(max)
Auto Refresh

PD Self Refresh Entry l P D V* 2 tQ P D H LQS/UQS (output) lC K D LOW
Hi-Z

DQ (output)
Hi-Z Qx
Note : 1. is don't care. 2. P D must be brought to "Low" within the timing between t F P D L (min) and t F P D L (max) to Self R e f r e s h m o d e . W h e n PD is brought to "Low" after I P D V , K 4 C 8 9 1 8 3 A D perform Auto Refresh and enter Power down mode. 3. It is desirable that clock input is continued at least I C K D f r o m R E F c o m m a n d e v e n t h o u g h P D is brought to "Low" for Self-Refresh Entry.

Self-Refresh Exit Timing
Unidirectional DS/QS mode 0 CLK CLK
*2
1
3
m1 -
m
m1 +
m2 +
n-1
n
n+1
p-1
p

lR E F C
*3

lR E F C
C o m m a n d ( 1 s t ) *6 C o m m a n d ( 2 n d ) *6

Command
DESL
WRA
*5
REF
*5
DESL
RDA*7
L A L* 7
l P D A =2 c y c l e s
*4
l R C D = 1cycle
l R C D = 1cycle
PD
tP D E X lL O C K

LQS/UQS (output)
Hi-Z
LOW
DQ (output)
Hi-Z

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Self-Refresh Exit Note : 1. is don't care. 2. Clock should be stable prior to PD = "High" if clock input is suspended in Self-Refresh mode. 3 . D E S L c o m m a n d m u s t b e a s s e r t e d d u r i n g I R E F C after P D is brought to "High" 4. l P D A is defined from the first clock rising edge after PD is brought to "High" 5. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any other operation. 6. Any command (except Read command) can be issued after lR E F C . 7. Read command (RDA +LAL) can be issued after lL C O K .
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K4C89363AF
Self-Refresh Entry Timing
Unidirectional DS/Free Running QS mode 0 CLK CLK l R C D =1cycle lR E F C 1 2 3 4 5 m1 m m+1

Command
WRA tF P D L
REF tFPDL
DESL
(min)
(max)
Auto Refresh

PD Self Refresh Entry l P D V* 2 tQ P D H lC K D LQS/UQS (output)

Hi-Z
DQ (output)
Hi-Z

Qx
Note : 1. is don't care. 2. P D must be brought to "Low" within the timing between t F P D L (min) and t F P D L (max) to Self R e f r e s h m o d e . W h e n P D is brought to "Low" after IP D V , K 4 C 8 9 1 8 3 A D p e r f o r m A u t o R e f r e s h a n d e n t e r Power down mode. 3. It is desirable that clock input is continued at least I C K D f r o m R E F c o m m a n d e v e n t h o u g h P D is brought to "Low" for Self-Refresh Entry.
Self-Refresh Exit Timing
Unidirectional DS/Free Running QS mode 0 CLK CLK 1 3 m1 m m1 + m2 + n-1 n n+1 p-1 p

lR E F C lR E F C

C o m m a n d ( 1 s t ) *6 C o m m a n d ( 2 n d ) *6

Command
DESL
WRA
*5
REF
*5
DESL
RDA*7
L A L* 7
l P D A =2 c y c l e s
*4
l R C D = 1cycle
l R C D = 1cycle
PD
tP D E X lL O C K

LQS/UQS QS (output)
DQ (output)
Hi-Z

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Self-Refresh Exit Note : 1. is don't care. 2. Clock should be stable prior to PD = "High" if clock input is suspended in Self-Refresh mode. 3 . D E S L c o m m a n d m u s t b e a s s e r t e d d u r i n g I R E F C after P D is brought to "High" 4. l P D A is defined from the first clock rising edge after PD is brought to "High" 5. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any other operation. 6. Any command (except Read command) can be issued after lR E F C . 7 . R e a d c o m m a n d ( R D A + L A L ) c a n b e i s s u e d a f t e r l L O C K. 8. QS output is invalid until DLL lock from Self-Refresh exit.
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K4C89363AF
Function Description
Network - DRAM
Network - DRAM is an acronym of Double Data Rate Network - DRAM. Network - DRAM is competent to perform fast random core access, low latency and high-speed data transfer.
Pin Functions
Clock Inputs : CLK & CLK
The CLK and C L K inputs are used as the reference for synchronous operation. CLK is master clock input. The C S, FN and all address input signals are sampled on the crossing of the positive edge of CLK and the negative edge of CLK . The QS and DQ output data are aligned to the crossing point of CLK and C L K . The timing reference point for the differential clock is when the CLK and C L K signals cross during a transition.
Power Down : PD
T h e PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a Clock Suspend function like a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into low state if any Read or Write operation is being performed.
Chip Select & Function Control : C S & FN
The C S and FN inputs are a control signal for forming the operation commands on Network-DRAM. Each operation mode is decided by the combination of the two consecutive operation commands using the C S and FN inputs.
Bank Addresses : BA0 & BA1
The BA0 and BA1 inputs are latched at the time of assertion of the RDA or WRA command and are selected the bank to be used for the operation. BA0 and BA1 also define which mode register is loaded during the Mode Register Set command (MRS or EMRS). BA0 Bank #0 Bank #1 Bank #2 Bank #3 0 1 0 1 BA1 0 0 1 1
Address Inputs : A0 to A14
A d d r e s s i n p u t s a r e u s e d t o a c c e s s t h e a r b i t r a r y a d d r e s s o f t h e m e m o r y c e l l a r r a y w i t h i n e a c h b a n k . T h e U p p e r A d d r e s s e s w i t h B an k address are latched at the RDA or WRA command and the Lower Addresses are latched at the LAL command. The A0 to A14 inputs are also used for setting the data in the Regular or Extended Mode Register set cycle.
Upper Address K4C89363AF
A0 to A14
Lower Address
A0 to A6
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Functional Description (Continued)
Data Input/Output : DQ0 ~ DQ35
The input data of DQ0 to DQ35 are taken in synchronizing with the both edges of LDS/UDS input signal. The output data of DQ0 to DQ35 are outputted synchronizing with the both edges of LQS/UQS output signal.
Data Strobe : DS(LDS/UDS) or QS(LQS/UQS)
Method of data strobe is chosen by Extended mode register.
(1) Unidirectional DS/QS mode DS is input signal and QS is output signal. Both edges of DS are used to sample all DQs at Write operation. Both edges of QS are used for trigger signal of all DQs at Read operation. During Write, Auto-Refresh and NOP cycle, QS assert always "Low" level. QS is Hi-Z in Self-Refresh mode.
(2) Unidirectional DS/Free running QS mode DS is input signal and QS is output signal. Both edges of DS are used to sample all DQs at Write operation. Both edges of QS are used for trigger signal of all DQs at Read operation. QS assert always toggle signal except Self-Refresh mode. This strobe type is easy to use for pin to pin connect application.
P o w e r S u p p l y : V D D , V D D Q , V SS , V S S Q
V D D a n d V SS a r e s u p p l y p i n s f o r m e m o r y c o r e a n d p e r i p h e r a l c i r c u i t s . V DDQ a n d V S S Q a r e p o w e r s u p p l y p i n s f o r t h e o u t p u t b u f f e r .
Reference Voltage : V REF
V REF is reference voltage for all input signals.
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K4C89363AF
Command Functions and Operations
K4C89363AF is introduced the two consecutive command input method. Therefore, except for Power Down mode, each operation mode decided by the combination of the first command and the second command from stand-by states of the bank to be accessed.
Read Operation (1st command + 2nd command = RDA + LAL)
Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in a read mode. When the LAL command with Lower Addresses is issued at the next clock of the RDA command, the data is read out sequentially synchronizing with the both edges of QS output signal (Burst Read Operation). The initial valid read data appears a fter C A S latency, the burst length of read data and the burst type must be set in the Mode Register beforehand. The read operated bank g o e s b a c k a u t o m a t i c a l l y t o t h e i d l e s t a t e a f t e r I RC.
Write Operation (1st command + 2nd command = WRA + LAL)
Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in a write mode. When the LAL command with Lower Addresses is issued at the next clock of the WRA command, the input data is latched sequentially synchronizing with the both edges of DS input signal (Burst Write Operation). The data and DS inputs have to be asserted in keeping with clock input after C A S latency-1 from the issuing of the LAL command. The DS have to be provided for a burst length. The C A S latency and the burst type must be set in the Mode Register beforehand. The write operated bank goes back automatically to the idle state after IRC. W r i t e B u r s t L e n g t h i s c o n t r o l l e d b y V W 0 a n d V W 1 i n p u t s w i t h L A L c o m m a n d . S e e V W t r u t h t a b l e .
Auto-Refresh Operation (1st command + 2nd command = WRA + REF)
K4C89363AF is required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with the REF command following to the WRA command. The Auto-Refresh mode can be effective only when all banks are in the idle state and all DQ are in Hi-Z states. In a point to notice, the write mode started with the WRA command is canceled by the REF command having gone into the next clock of the WRA command instead of the LAL command. The minimum period between the Auto-Refresh command and the next command is specified by IREFC. H o w e v e r , a b o u t a s y n t h e t i c a v e r a g e i n t e r v a l o f A u t o - R e f r e s h c o m m a n d , i t m u s t b e c a r e f u l . I n c a s e o f e q u a l l y d i s tributed refresh, Auto-Refresh command has to be issued within once for every 3.9 us by the maximum In case of burst refresh or random distributed refresh, the average interval of eight consecutive Auto-Refresh command has to be more than 400ns always. In oth er words, the number of Auto-Refresh cycles which can be performed within 3.2 us (8x400ns) is to 8 times in the maximum.
Self-Refresh Operation (1st command + 2nd command = WRA + REF with PD ="L")
It is the function of Self-Refresh operation that refresh operation can be performed automatically by using an internal timer. When all banks are in the idle state and all outputs are in Hi-z states, the K4C89363AF become Self-Refresh mode by issuing the Self-Refresh c o m m a n d . P D h a s t o b e b r o u g h t t o " L o w " w i t h i n t FPDL f r o m t h e R E F c o m m a n d f o l l o w i n g t o t h e W R A c o m m a n d f o r a S e l f - R e f r e s h m o d e entry. In order to satisfy the refresh period, the Self-Refresh entry command should be asserted within 3.9us after the latest AutoR e f r e s h c o m m a n d . O n c e t h e d e v i c e e n t e r s S e l f - R e f r e s h m o d e , t h e D E S L c o m m a n d m u s t b e c o n t i n u e d f o r I REFC period. In addition, it is desirable that clock input is kept in ICKD period. The device is in Self-Refresh mode as long as P D held "Low". During Self-Refresh mode, all input and output buffers except for PD are disabled, therefore the power dissipation lowers. Regarding a Self-Refresh mode exit, P D h a s t o b e c h a n g e d o v e r f r o m " L o w " t o " H i g h " a l o n g w i t h t h e D E S L c o m m a n d , a n d t h e D E S L c o m m a n d h a s t o b e c o n t i n u o u s l y i s s u e d i n t h e n u m b e r o f c l o c k s s p e c i f i e d b y I REFC . The Self-Refresh exit function is asynchronous operation. It is required that one A u t o - R e f r e s h c o m m a n d i s i s s u e d t o a v o i d t h e v i o l e n c e o f t h e r e f r e s h p e r i o d j u s t a f t e r I REFC from Self-Refresh exit.
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K4C89363AF
Power Down Mode( P D="L" )
When all banks are in the idle state and all DQ outputs are in Hi-Z states, the K4C89363AF become Power Down Mode by asserting PD is "Low". When the device enters the Power Down Mode, all input and output buffers except for PD , CLK, C L K and QS. Therefore, the power dissipation lowers. To exit the Power Down Mode, PD has to be brought to "High" and the DESL command has to be issued for IP D A c y c l e a f t e r P D g o e s h i g h . T h e P o w e r D o w n e x i t f u n c t i o n i s a s y n c h r o n o u s o p e r a t i o n .
Mode Register Set (1st command + 2nd command = RDA + MRS)
When all banks are in the idle state, issuing the MRS command following to the RDA command can program the Mode Register. In a point to notice, the read mode started with the RDA command is canceled by the MRS command having gone into the next clock of the RDA command instead of the LAL command. The data to be set in the Mode Register is transferred using A0 to A14, BA0 and BA1 address inputs. The K4C89363AF have two mode registers. These are Regular and Extended Mode Register. The Regular or Extended Mode Register is chosen by BA0 and BA1 in the MRS command.The Regular Mode Register designates the operation mode for a read or write cycle. The Regular Mode Register has four function fields.
The four fields are as follows : (R-1) Burst Length field to set the length of burst data (R-2) Burst Type field to designate the lower address access sequence in a burst cycle (R-3) C A S Latency field to set the access time in clock cycle (R-4) Test Mode field to use for supplier only.
The Extended Mode Register has two function fields. The two fields are as follows: (E-1) DLL Switch field to choose either DLL enable or DLL disable (E-2) Output Driver Impedance Control field. (E-3) Data Strobe Select
Once these fields in the Mode Register are set up, the register contents are maintained until the Mode Register is set up again b y another MRS command or power supply is lost. The initial value of the Regular or Extended Mode Register after power-up is undefined, therefore the Mode Register Set command must be issued before proper operation.
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K4C89363AF
* Regular Mode Register/Extended Mode Register change bits (BA0, BA1) These bits are used to choose either Regular MRS or Extended MRS
BA1
0 0 1
BA0
0 1 X
A14~A0
Regular MRS cycle Extended MRS cycle Reserved
Regular Mode Register Fields
(R-1) Burst Length field (A2 to A0) This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 2 or 4 words.
A2
0 0 0 0 1 (R-2) Burst Type field (A3)
A1
0 0 1 1 X
A0
0 1 0 1 X
Burst Length
Reserved 2 words 4 words Reserved Reserved
This Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is " 0", Sequential mode is selected. When the A3 bit is "1", Interleave mode is selected. Both burst types support burst length of 2 and 4 words.
A3
0 1 * Addressing sequence of Sequential mode (A3)
Burst Type
Sequential Interleave
A column access is started from the inputted lower address and is performed by incrementing the lower address input to the device.
C A S Latency = 4 (Free Running QS mode) CK CK Command RDA LAL
QS
DQ
Data 0 Data 1 Data 2 Data 3
Addressing sequence for Sequential mode Data
Data 0 Data 1 Data 2 Data 3
Access Address
n
Burst Length
2 words (Address bits is LA0)
n+1 n+2 n+3
not carried from LA0~LA1 4 words(Address bits is LA1, LA0) not carried from LA1~LA2
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K4C89363AF
Functional Description (Continued)
* Addressing sequence of Inteleave mode A column access is started from the inputted lower address and is performed by interleaving the address bits in the sequence shown as the following.
Addressing sequence for Interleave mode Data
Data 0 Data 1 Data 2 Data 3 (R-3) C A S Latency field (A6 to A4) This field specifies the number of clock cycles from the assertion of the LAL command following the RDA command to the first data read. The minimum values of C A S Latency depends on the frequency of CLK. In a write mode, the place of clock which should input write data is C A S Latency cycles - 1.
Access Address
...A8 A7 A6 A5 A4 A3 A2 A1 A0 ...A8 A7 A6 A5 A4 A3 A2 A1 A 0 ...A8 A7 A6 A5 A4 A3 A2 A 1 A 0 ...A8 A7 A6 A5 A4 A3 A2 A 1 A 0
Burst Length
2 words
4 words
Addressing sequence for Interleave mode A6
0 0 0 0 1 1 1 1
A5
0 0 1 1 0 0 1 1
A4
0 1 0 1 0 1 0 1
CAS
Latency
Reserved Reserved Reserved Reserved 4 5 6 Reserved
(R-4) Test Mode field (A7) This bit is used to enter Test Mode for supplier only and must be set to "0" for normal operation.
(R-5) Reserved field in the Regular Mode Register * Reserved bits (A8 to A14) These bits are reserved for future operations. They must be set to "0" for normal operation.
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K4C89363AF
Extended Mode Register Fields
(E-1) DLL Switch field (A0) This bit is used to enable DLL. When the A0 bit is set "0", DLL is enabled. (E-2) Output Driver Impedance Control field (A1 to A4) This field is used to choose Output Driver Strength. Four types of Driver Strength are supported. QS and DQ Driver Strength can be chosen separately. A2-A1 specified the DQ Driver Strength. A4-A3 specified the QS Driver Strength.
QS A4
0 0 1 1 (E-3) Strobe Select (A6/A5)
DQ Output Driver Impedance Control A3
0 1 0 1
A2
0 0 1 1
A1
0 1 0 1 Normal Output Driver Strong Output Driver Weaker Output Driver Reserved
Two types of strobe are supported. This field is used to choose the type of data strobe. (1) Unidirectional DS/QS mode Data strobe is separated DS for write strobe and QS for read strobe. DS is used to sample write data at write operation. QS is aligned with read data at Read operation. (2) Unidirectional DS/Free running QS mode Data strobe is separated DS for write strobe and QS for read strobe. DS is used to sample write data at write operation. QS is aligned with read data and always clocking
A6
0 0 1 1 (E-4)Reserved fied (A7 to A14)
A5
0 1 0 1
Strobe Select
Reserved Reserved Unidirectional DS/QS mode Unidirectional DS/Free running QS mode
These bits are reserved for future operations and must be set to "0" for normal operation.
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K4C89363AF
Package Outline Drawing (FBGA 144ball, 1.0 x 0.8 mm) - will be added
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K4C89363AF
General Information
Organization 288M(x32) 288M(x36) F6 (667Mbps) K4C89323AF-GCF6 K4C89363AF-GCF6 FB (600Mbps ) K4C89323AF-GCFB K4C89363AF-GCFB F5 (500Mbps ) K4C89323AF-GCF5 K4C89363AF-GCF5
1
2
3
4
5
6
7
8
9
10
11
K 4 C XX XX X X X
Memory DRAM
- X X XX
Speed
Temperature & Power Small Classification Density and Refresh Organization Bank Package
Version
Interface (VDD & VDDQ)
1. SAMSUNG Memory 2. DRAM : 4 3. Small Classification C : Network-DRAM
:K
8. Version F : 7th Generation
9. P a c k a g e T : TSOP II (400mil x 875mil) G : 144 FBGA 10. Temperature & Power
4. Density & Refresh 89 : 288M 8K/32ms
5. Organization 32 36 : x32 : x36
C : (Commercial, Normal)
11. Speed F6 : 667Mbps/pin (333MHz, CL=6)
6. Bank 3 : 4 Bank 7. Interface (VDD & VDDQ) A: SSTL-2(2.5V, 1.8V)
FB : 600Mbps /pin (300MHz, CL=6) F5 : 500Mbps/pin (250MHz, CL=6)
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